1. Field of the Invention
The present invention relates in general to a CCD image sensor, and more particularly to a CCD image sensor of interlaced scanning type.
2. Description of the Prior Art
Generally, a CCD is believed to be an active device for transferring, under a control of a clock pulse a signal charge corresponding to incident light incoming along a predetermined path and has typically been used in image processing devices, such as, for example, a storage device, a logic element, a CCD image sensor, etc.
The scanning of the CCD image sensor employing the CCD is typically of either an interlaced scanning type or a non-interlaced scanning type.
In non-interlaced scanning, there is provided one picture, i.e., one frame containing a plurality of fields, with the scanning on the screen beginning with data in the first input field, as shown in FIG. 1A.
In FIG. 1A, the display of each of fields on the screen in their input orders are designated as the numerals 1, 2, 3. On the other hand, in interlaced scanning, there is provided one frame containing a plurality of even fields and a plurality of odd fields, with the scanning on the screen beginning with data in the odd field, as shown in FIG. 1B.
In FIG. 1B, the numeral 1 designates each of the odd fields and the numeral 2 designates each of the even fields.
Therefore, in non-interlaced scanning, the scanning rate is fast, so such that the actual image of a fast moving object can be picked up accurately. For this reason, the noninterlaced scanning may be applied to a military equipment, such as missile tracking equipment.
However, a problem with this non-interlaced scanning is that the image shakes on the screen.
For interlaced scanning, there is provided a sense of stability of the image in that the scanning rate is slower than that in non-interlaced scanning, but a fast moving object appears as two images. For this reason, interlaced scanning is inappropriate for military purposes and typically is applied to a television broadcasting system, such as a NTSC system or a
system, for the scanning of an image on the screen.
Construction of a conventional CCD image sensor of the interlaced scanning type is discussed with reference to FIGS. 2A through 2D below.
With reference to FIG. 2A, there is shown a schematic diagram of the construction of a conventional CCD image sensor of the interlaced scanning type. A conventional CCD image sensor comprises an N type horizontal charge coupled device (HCCD) region and a plurality of N type vertical charge coupled device (VCCD) regions, to each of which a series of N type photodiodes PD are connected. Each of the N type photodiodes PD is connected to an N type VCCD region such that an image signal charge output therefrom is transferred to the N type VCCD region in a single direction. Also, the N type VCCD regions are connected to the N type HCCD region, such that the signal charges transferred from the photodiodes PD are transferred to the N type HCCD region simultaneously in response to first to fourth VCCD clock signals V.phi.1-V.phi.4, one clock signal corresponding to one phase.
With reference to FIG. 2B, there is shown a layout diagram of the construction of the conventional CCD image sensor in FIG. 2A. The CCD image sensor comprises a channel stop region ST, formed between each of the N type VCCD regions and each of the N type photodiodes PD. An odd gate electrode PG1 is formed over each of the N type VCCD regions and each of the channel stop regions ST such that it is connected to each of transfer gates TG1 of the N type photodiodes PD arranged on an odd horizontal line, the odd gate electrode PG1 being supplied with the first and the second clock signals V.phi.1-V.phi.2. On the other hand, an even gate electrode PG2 is formed over each of the channel stop regions ST, each of the N type VCCD regions and each of the N type photodiodes PD, such that it is connected to each of transfer gates TG2 of the N type photodiodes PD arranged on an even horizontal line, the even gate electrode PG2 being supplied with the third and the fourth clock signals V.phi.3-V.phi.4.
Forming of the odd gate electrode PG1 and the even gate electrode PG2 may be repeated successively, as required by a layout of the CCD image sensor, in the same form. Also, these electrodes PG1 and PG2 are generally electrically isolated from each other by a region (not shown) of an insulating material, such as silicon oxide.
On the other hand, materials of the transfer gates TG1 and TG2 and the odd and even gate electrodes PG1 and PG2 may be polysilicon.
The odd gate electrode PG1 includes a first odd gate electrode PG1a formed under each of the N type photodiodes PD on the odd horizontal line and a second odd gate electrode PG1b formed over each of the N type photodiodes PD on the odd horizontal line and connected to each of the transfer gates TG1 of the photodiodes PD on the odd horizontal line, the first odd gate electrode PG1a being supplied with the second VCCD clock signal V.phi.2 and the second odd gate electrode PG1b being supplied with the first VCCD clock signal V.phi.1.
The even gate electrode PG2 includes a first even gate electrode PG2a formed under each of the N type photodiodes PD on the even horizontal line and a second even gate electrode PG2b formed over each of the N type photodiodes PD on the even horizontal line and connected to each of the transfer gates TG2 of the photodiodes PD on the even horizontal line, the first even gate electrode PG2a being supplied with the fourth VCCD clock signal V.phi.4 and the second even gate electrode PG2b being supplied with the third VCCD clock signal V.phi.3.
Also, the first through the fourth VCCD clock signals V.phi.1-V.phi.4 of four phases corresponds to two fields, i.e. an even field and an odd field. The clocking operation of the N type VCCD region will be described hereinafter in more detail.
With reference to FIG. 2C, there is shown a sectional view, taken on the line a--a' of FIG. 2B. A conventional CCD image sensor comprises an N type substrate 100 and a P type well 200, formed on the N type substrate 100. Also on the N type substrate 100 are configured a series of arrangements that the N type photodiode PD and the N type VCCD region on the even horizontal line are connected to each other at a desired interval via the channel stop region ST. Each of the transfer gates TG2 is formed over and between each of the N type photodiodes PD and each of the N type VCCD regions to connect them with each other. Also over the surface of each of the N type VCCD regions is formed a second even gate electrode PG2b being supplied with the third VCCD clock signal V.phi.3, to be connected to each of the transfer gates TG2 of the N type photodiodes PD arranged on the even horizontal line.
Herein, the p type well 200 is comprised of two types, a shallow P type well 200a and a deep P type well 200b, for control of over flow drain (OFD) voltage.
On the surface of each of the N type photodiodes PD is generally formed a P.sup.+ type thin layer 300 for application of an initial bias. In FIG. 2C, the lower side of the channel stop region ST designated as the character P.sup.+, indicates a channel stop ion region.
Referring to FIG. 2D, there is shown a sectional view, taken on the line b--b' of FIG. 2B. The P type well 200 is formed on the N type substrate 100, identically to FIG. 2C. Also on the N type substrate 100 are configured a series of N type photodiode PD regions and N type VCCD regions on an even horizontal line connected to each other at desired intervals via channel stop region ST. Also, over the surface of each of the N type VCCD regions is formed a first even gate electrode PG2a supplied with the fourth VCCD clock signal V.phi.4.
Similarly, on the surface of each of the N type photodiodes PD is generally formed a P.sup.+ type thin layer 300 for application of an initial bias. In FIG. 2D, the lower side of the channel stop region ST, designated by the character P.sup.+, indicates a channel stop ion region. Herein, the P type well 200 is comprised of a shallow P type well 200a and a deep P type well 200b, for the control of over flow drain (OFD) voltage.
Hence, the transfer gate TG1 of each of the N type photodiodes PD, arranged on an odd horizontal line, is driven only by the first VCCD clock signal V.phi.1 applied to the second odd gate electrode PG1b, and the transfer gate TG2 of each of the N type photodiodes PD, arranged on an even horizontal line, is driven only by the third VCCD clock signal V.phi.3 applied to the second even gate electrode PG2b.
The second VCCD clock signal V.phi.2, applied to the first odd gate electrode PG1a and the fourth VCCD clock signal V.phi.4, applied to the first even gate electrode PG2a, serve merely to transfer image signal charges traveling from the N type photodiodes PD arranged on the odd and even horizontal lines toward the HCCD region.
Now, the operation of a conventional CCD image sensor of the above-mentioned construction will be described with reference to FIGS. 3A through 3D.
With reference to FIG. 3A, there is shown a timing diagram of the first through fourth VCCD clock signals V.phi.1-V.phi.4 of four phases, each including two fields, an even field and an odd field.
In FIG. 3A, in the odd field of the first VCCD clock signal V.phi.1 of tri-state levels, applied to the second odd gate electrode PG1b is contained a transfer gate drive voltage VI of high level (15V). Also, in the even field of the third VCCD clock signal V.phi.3 applied to the second even gate electrode PG2b is contained a transfer gate drive voltage V2 of high level (15V).
If the first through fourth VCCD clock signals V.phi.1-V.phi.4 in the odd field are supplied simultaneously, the transfer gates TG1 of the N type photodiodes PD arranged on each of the odd horizontal lines are turned on simultaneously by the transfer gate drive voltage VI contained in the first VCCD clock signal V.phi.1.
For this reason, the image signal charges produced from the N type photodiodes PD are transferred to the N type VCCD regions, to potential pockets formed under the second odd gate electrodes PG2b as shown in FIG. 3C. and then toward the N type HCCD region by the VCCD clocking operation.
FIG. 3B is a pulse waveform diagram of the first through fourth clock signals V.phi.1-V.phi.4 at the unit interval K of FIG. 3A. The image signal charges produced from the N type photodiodes PD are transferred vertically toward the N type HCCD region by a series of clocking operations, as shown in FIG. 3B.
At this time, the second VCCD clock signal V.phi.2, supplied through the first odd gate electrode PG1a formed in the lower side of the odd horizontal line, serves merely to transfer the image signal charges transferred from the N type photodiodes PD arranged on the even horizontal line by the first VCCD clock signal V.phi.1 to the N type HCCD region, together with the first VCCD clock signal V.phi.1.
Thereafter, if the first through the fourth VCCD clock signals V.phi.1-V.phi.4 in the even field in FIG. 3A are supplied simultaneously, the transfer gates TG2 of the N type photodiodes PD arranged on each of the even horizontal lines are turned on simultaneously by the transfer gate drive voltage V2 contained in the third VCCD clock signal V.phi.3.
As a result, the image signal charges produced from the N type photodiodes PD on the even horizontal line are transferred to the N type VCCD regions and then toward the N type HCCD region by the VCCD clocking operation, as shown in FIG. 3B, in the same manner as that of the odd field. At this time, the signal charges transferred from the photodiodes PD on the even horizontal lines are gathered with the signal charges transferred from the photodiodes PD on the odd horizontal lines in potential pockets formed under the second even gate electrodes PG2b, as shown in FIG. 3C, by the odd gate electrodes PG1, and then the gathered signal charges are transferred toward the HCCD region.
At this time, the fourth VCCD clock signal V.phi.4, supplied through the first even gate electrode PG2a of the even gate electrode PG2 formed in the lower side of the even horizontal line, serves merely to transfer the image signal charges transferred from the N type photodiodes PD arranged on the even horizontal line by the third VCCD clock signal V.phi.3 to the N type HCCD region, together with the third VCCD clock signal V.phi.3.
As stated, the use of VCCD clock signals of four phases has the effect of transferring more of the image signal charge than would use of VCCD clock signals of two phases.
As a result, as mentioned above, application of VCCD clocking signals of four phases, i.e. the first through fourth VCCD clock signals V.phi.1-V.phi.4 as shown in FIG. 3A, the image signal charges from the N type photodiodes PD arranged in the odd horizontal line are scanned first in sequence on the screen through the N type VCCD regions and then through the N type HCCD region and then the image signal charges from the N type photodiodes PD, arranged in the even horizontal line are scanned in sequence on the screen through the N type VCCD regions and then through the N type HCCD region.
As previously stated, the scanning of the CCD image sensor as mentioned above is usually referred to as an interlaced scanning type.
With reference to FIG. 3D, there is shown a pixel format of one picture, or one frame, the picture being comprised of pixels, each being displayed as the numerals 1 and 2, each designating the image signal charges from the N type photodiodes PD arranged in odd and even horizontal lines as shown in FIG. 2A, respectively.
In result, as mentioned above, a conventional CCD image sensor of the interlaced scanning type has an advantage, in that the image signal charges can be transferred at high speed by the four phase clocking operation.
However, a conventional CCD image sensor of the interlaced scanning type also has disadvantages as follows:
First, the photodiodes PD arranged on the odd and even horizontal lines comprise respective typical color filters formed thereon to output different chrominance signals. For this reason, in a case where the different chrominance signals outputted from the photodiodes PD arranged on the odd and even horizontal lines are collected to produce a new chrominance signal and the new chrominance signal is then transferred toward the HCCD region, an additional apparatus is required for mixing the chrominance signals outputted from the photodiodes PD arranged on the odd and even horizontal lines.
Second, the VCCD region driving clock signals are as many as four in number, resulting in complexity of the driving system. Also, four gate electrodes are required to apply the four clock signals, corresponding to the number of the clock signals, thereby resulting in complexity in construction of the conventional CCD image sensor of the interlaced scanning type.